With ever increasing demands to reduce both the size of devices and their power consumption, it is becoming increasingly challenging to design robust semiconductor memories such as SRAM. As technology scales down the SRAM bitcell is losing margin in both the read and write operations due to variations in threshold voltages of the tiny devices used in the bit cell.
Each storage cell in an SRAM comprises a feedback loop for holding a data value. In order to write to the feedback loop and store a new value, the input data value must have a high enough voltage level to be able to switch the state stored by the feedback loop if required, while reading from the feedback loop should be performed without disturbing the values stored in any of the feedback loops. When reading from a cell both bit lines are pre-charged and the side of the cell storing a 0 will pull down the bit line it is connected to and this change in voltage level can be detected to determine where the 0 is stored. However, the difference in voltage levels between the precharged bit line and the 0 may result in the node storing a 0 being pulled up towards 1 resulting in instability in the bit cell and the bit cell flipping value. This is called read disturb and can happen to a cell during a read to a cell or during a write to another cell on the same word line. In the latter case the word line is activated to access the cell being written to, which affects other cells connected to the word line.
One way of improving read and write performance is by effecting changes on the wordline signal, the bitline signal or a column power source. Increasing the voltage on the wordline slowly in response to a data access request allows the voltage level on non-driven bitlines to decay due to bitline leakage and column effects and to discharge due to the bitcell pulling down on the bitline if a 0 was stored thus resisting at least to some extent the charge injection from the precharged bitline through the pass gate which is slowly being turned on. The theory is that the bitcell pulldown should be stronger than the weak pass gate that is injecting charge as soon as its gate is turned on by the signal on the wordline. This decreases the chances of the charge on the bitlines being sufficient to flip a cell that is not being written to, but it delays the data access and therefore lowers performance.
It would be desirable to be able to reduce both read and write failures of a semiconductor memory without unduly affecting performance.